./cad/iverilog, Verilog simulation and synthesis tool (stable release version)

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Branch: CURRENT, Version: 10.1.1, Package name: iverilog-10.1.1, Maintainer: dmcmahill

Icarus Verilog is intended to compile ALL of the Verilog HDL as described in
the IEEE-1364 standard. Of course, it's not quite there yet. It does currently
handle a mix of structural and behavioral constructs.

Icarus Verilog is not aimed at being a simulator in the traditional sense, but
a compiler that generates code employed by back-end tools.


Required to build:
[devel/gperf]

Master sites:

SHA1: 7f4cead8cabb90cc4525951357c43866ca710749
RMD160: 77c933b712ab027b13a81e3eead7ee4f565741b7
Filesize: 1645.435 KB

Version history: (Expand)


CVS history: (Expand)


   2016-10-09 01:01:46 by Kamil Rytarowski | Files touched by this commit (8) | Package updated
Log message:
Import iverilog (Icarus Verilog) 10.1.1 as cad/iverilog

It's a rename of cad/verilog to a better name.

Updated DESCR for new package:

Icarus Verilog is intended to compile ALL of the Verilog HDL as described in
the IEEE-1364 standard. Of course, it's not quite there yet. It does currently
handle a mix of structural and behavioral constructs.

Icarus Verilog is not aimed at being a simulator in the traditional sense, but
a compiler that generates code employed by back-end tools.

No objections to rename from <gdt>