./cad/verilator, Verilog HDL simulator

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Branch: CURRENT, Version: 4.012, Package name: verilator-4.012, Maintainer: ryoon

Verilator is the fastest free Verilog HDL simulator, and outperforms
most commercial simulators. Verilator compiles synthesizable
SystemVerilog (generally not test-bench code), plus some SystemVerilog
and Synthesis assertions into single- or multithreaded C++ or
SystemC code. Verilator is designed for large projects where fast
simulation performance is of primary concern, and is especially
well suited to generate executable models of CPUs for embedded
software design teams.


Required to build:
[devel/flex] [pkgtools/cwrappers]

Master sites:

SHA1: 653688c0dc8521d8d3ab9f9e94180f2271ec08ff
RMD160: d15a54b8243caf5e22c3f9c6f6ff76ee7a37219b
Filesize: 2454.403 KB

Version history: (Expand)


CVS history: (Expand)


   2019-04-01 14:22:53 by Ryo ONODERA | Files touched by this commit (3) | Package updated
Log message:
Update to 4.012

* flex from NetBSD base causes build failure, so use pkgsrc/devel/flex instead.

Changelog:
* Verilator 4.012 2019-3-23

***   Add +verilator+seed, bug1396. [Stan Sokorac]

***   Support $fread.  [Leendert van Doorn]

***   Support void' cast on functions called as tasks, bug1383. [Al Grant]

***   Add IGNOREDRETURN warning, bug1383.

****  Report PORTSHORT errors on concat constants, bug 1400. [Will Korteland]

****  Fix VERILATOR_GDB being ignored, msg2860. [Yu Sheng Lin]

****  Fix $value$plus$args missing verilated_heavy.h. [Yi-Chung Chen]

****  Fix MSVC compile error, bug1406. [Benjamin Gartner]

****  Fix maintainer test when no Parallel::Forker, msg2630. [Enzo Chi]

****  Fix +1364-1995ext flags applying too late, bug1384. [Al Grant]

* Verilator 4.010 2019-01-27

***   Removed --trace-lxt2, use --trace-fst instead.

****  For --xml, add additional information, bug1372. [Jonathan Kimmitt]

****  Add circular typedef error, bug1388.  [Al Grant]

****  Add unsupported for loops error, msg2692. [Yu Sheng Lin]

****  Fix FST tracing of wide arrays, bug1376. [Aleksander Osman]

****  Fix error when pattern assignment has too few elements, bug1378. [Viktor Tomov]

****  Fix error when no modules in $unit, bug1381. [Al Grant]

****  Fix missing too many digits warning, bug1380. [Jonathan Kimmitt]

****  Fix uninitialized data in verFiles and unroller, bug1385. bug1386. [Al Grant]

****  Fix internal error on xrefs into unrolled functions, bug1387. [Al Grant]

****  Fix DPI export void compiler error, bug1391. [Stan Sokorac]

* Verilator 4.008 2018-12-01

***   Support "ref" and "const ref" pins and functions, \ 
bug1360. [Jake Longo]

***   In --xml-only show the original unmodified names, and add module_files
      and cells similar to Verilog-Perl, msg2719. [Kanad Kanhere]

****  Add CONTASSREG error on continuous assignments to regs, bug1369. [Peter Gerst]

****  Add PROCASSWIRE error on behavioral assignments to wires, msg2737. [Neil \ 
Turton]

****  Add IMPORTSTAR warning on import::* inside $unit scope.

****  Fix --trace-lxt2 compile error on MinGW, msg2711. [HyungKi Jeong]

****  Fix hang on bad pattern keys, bug1364. [Matt Myers]

****  Fix crash due to cygwin bug in getline, bug1349. [Affe Mao]

****  Fix __Slow files getting compiled with OPT_FAST, bug1370. [Thomas Watts]
   2018-12-16 10:05:13 by Ryo ONODERA | Files touched by this commit (5)
Log message:
cad/verilator: import verilator-4.006

Verilator is the fastest free Verilog HDL simulator, and outperforms
most commercial simulators. Verilator compiles synthesizable
SystemVerilog (generally not test-bench code), plus some SystemVerilog
and Synthesis assertions into single- or multithreaded C++ or
SystemC code. Verilator is designed for large projects where fast
simulation performance is of primary concern, and is especially
well suited to generate executable models of CPUs for embedded
software design teams.