./wip/py-verilog, Python-based Hardware Design Processing Toolkit for Verilog HDL

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Branch: CURRENT, Version: 1.0.6, Package name: py37-verilog-1.0.6, Maintainer: jihbed.research



Required to run:
[devel/py-setuptools] [textproc/py-jinja2] [lang/python37]

Required to build:
[pkgtools/cwrappers]

Master sites:

SHA1: 6defce45d5047698503b1f401438b6e85d96abfd
RMD160: 4bfb304e822d4b188a072e8192ee190b309a0f8b
Filesize: 157.104 KB

Version history: (Expand)