Next | Query returned 5 messages, browsing 1 to 10 | previous

History of commit frequency

CVS Commit History:


   2021-10-26 12:04:17 by Nia Alarie | Files touched by this commit (63)
Log message:
cad: Replace RMD160 checksums with BLAKE2s checksums

All checksums have been double-checked against existing RMD160 and
SHA512 hashes
   2021-10-07 15:20:33 by Nia Alarie | Files touched by this commit (63)
Log message:
cad: Remove SHA1 hashes for distfiles
   2020-05-20 08:09:10 by Roland Illig | Files touched by this commit (52)
Log message:
mark packages that fail with -Werror=char-subscripts

These packages are susceptible to bugs when confronted with non-ASCII
characters.

See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94182.

It takes some time to analyze and fix these individually, therefore they
are only marked as "needs work".
   2020-03-18 18:45:25 by Joerg Sonnenberger | Files touched by this commit (3)
Log message:
Not really C++11 ready. Don't define bool/true/false for C++.
   2016-10-09 15:14:06 by Kamil Rytarowski | Files touched by this commit (4)
Log message:
Import veriwell-2.8.7 as cad/veriwell

VeriWell is a full Verilog simulator. It supports nearly all of the
IEEE1364-1995 standard, as well as PLI 1.0.

Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in
the mid-1990 and was included with the Thomas and Moorby book.

Next | Query returned 5 messages, browsing 1 to 10 | previous