Log Message:
update to 20060124 snapshot.

A few new features have been added to allow proper simulation with
newer Xilinx UNISIM models. (They are starting to use Verilog 2001
features.) And also various bug fixes in this release.

-- Primitive and continuous assign delays can now be non-constant. This
   needed some new run-time support, so vvp had a slight format change,
   and certain new optimizations follow as a result.

-- Bug handling certain constant sub-expressions in concatenation
   expressions. Also, allow concat expressions in constant contexts.

-- Support for wide divide expressions.

-- Fixes for stubborn compilers.

-- Fix bugs in padding of signed expressions.

-- More fixes for following the data types of expressions.