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cad/MyHDL-gplcver,
GPL Cver cosimulation support for py-MyHDL
Branch: pkgsrc-2019Q3,
Version: 0.10,
Package name: MyHDL-gplcver-0.10,
Maintainer: pkgsrc-usersMyHDL is a Python package for using Python as a hardware
description language. Popular hardware description languages, like
Verilog and VHDL, are compiled languages. MyHDL with Python
can be viewed as a "scripting language" counterpart of such
languages. However, Python is more accurately described as a very
high level language (VHLL). MyHDL users have access to the
amazing power and elegance of Python for their modeling work.
This package is GPL Cver cosimulation support for py-MyHDL.
Required to run:[
cad/gplcver]
Required to build:[
pkgtools/cwrappers]
Master sites:
SHA1: d766a1a556e9dce23af07d1b378fbcc6e3b86494
RMD160: 234d3f3c5d2d84e548e317e1b85bc28efbfd7b14
Filesize: 1177.213 KB
Version history: (Expand)
- (2019-10-02) Package added to pkgsrc.se, version MyHDL-gplcver-0.10 (created)