NOTICE: This package has been removed from pkgsrc

./wip/verilog08, Verilog simulation and synthesis tool (old version of 0.8)

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Branch: CURRENT, Version: 0.8.7, Package name: verilog08-0.8.7, Maintainer: pkgsrc-users

Verilog-0.8 series has synthesize capability to xnf (Xilinx) and fpga(EDIF).

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
compiler, compiling source code writen in Verilog (IEEE-1364) into some target
format. For batch simulation, the compiler can generate C++ code that is
compiled and linked with a run time library (called "vvm") then executed as
a command to run the simulation. For synthesis, the compiler generates
netlists in the desired format.

The compiler proper is intended to parse and elaborate design descriptions
written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
complex standard, so it will take some time for it to get there, but that's
the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well,
and some -1999 features will creep in.


Required to run:
[devel/readline]

Required to build:
[devel/gperf]

Master sites:

SHA1: 814f12a99463a637cb13e0d86755f762c5d90270
RMD160: 63fb4f9e1e85157010d480e5d66513d6c9ac4326
Filesize: 1244.113 KB

Version history: (Expand)

CVS history: (Expand)


   2014-10-09 16:06:26 by Thomas Klausner | Files touched by this commit (97) 
Log message:
Remove pkgviews: don't set PKG_INSTALLATION_TYPES in Makefiles.
   2014-08-20 14:26:13 by Makoto Fujiwara | Files touched by this commit (1) 
Log message:
Seems OK to co-exists with cad/verilog, Makefile has to be adjusted.
   2014-08-20 14:16:39 by Makoto Fujiwara | Files touched by this commit (1) 
Log message:
Seems OK to co-exists with cad/verilog.
   2014-08-20 13:37:00 by Makoto Fujiwara | Files touched by this commit (21) 
Log message:
Import verilog08-0.8.7 as wip/verilog08.
Verilog 0.8 revived. Newer version said dropped the synthesis capability.
(This version was picked up 2009-03 of cad/verilog and added user-destdir
patches)

Verilog-0.8 series has synthesize capability to xnf (Xilinx)  and fpga(EDIF).

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
compiler, compiling source code writen in Verilog (IEEE-1364) into some target
format. For batch simulation, the compiler can generate C++ code that is
compiled and linked with a run time library (called "vvm") then executed as
a command to run the simulation. For synthesis, the compiler generates
netlists in the desired format.

The compiler proper is intended to parse and elaborate design descriptions
written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
complex standard, so it will take some time for it to get there, but that's
the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well,
and some -1999 features will creep in.