./cad/MyHDL-iverilog, Icarus Verilog cosimulation support for py-MyHDL

[ CVSweb ] [ Homepage ] [ RSS ] [ Required by ] [ Add to tracker ]

Branch: pkgsrc-2007Q3, Version: 0.5.1, Package name: MyHDL-iverilog-0.5.1, Maintainer: pkgsrc-users

MyHDL is a Python package for using Python as a hardware
description language. Popular hardware description languages, like
Verilog and VHDL, are compiled languages. MyHDL with Python
can be viewed as a "scripting language" counterpart of such
languages. However, Python is more accurately described as a very
high level language (VHLL). MyHDL users have access to the
amazing power and elegance of Python for their modeling work.

Master sites: (Expand)

SHA1: 4c98248be79ebb1a2c5de78aefd6c55c0675e47d
RMD160: 9802663d82c86098694d34783b7352e6f5435b20
Filesize: 750.468 KB

Version history: (Expand)