./cad/verilog, Verilog simulation and synthesis tool (stable release version)

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Branch: pkgsrc-2008Q2, Version: 0.8.3, Package name: verilog-0.8.3, Maintainer: dmcmahill

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
compiler, compiling source code writen in Verilog (IEEE-1364) into some target
format. For batch simulation, the compiler can generate C++ code that is
compiled and linked with a run time library (called "vvm") then executed as
a command to run the simulation. For synthesis, the compiler generates
netlists in the desired format.

The compiler proper is intended to parse and elaborate design descriptions
written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
complex standard, so it will take some time for it to get there, but that's
the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well,
and some -1999 features will creep in.


Required to build:
[devel/bison] [devel/gmake]

Master sites:

SHA1: c3fd64bcdc51d44bde1fd5e168cdff761057c798
RMD160: b45c7b9811f99ad833e6bf8e5508a72472b7b8f7
Filesize: 1531.378 KB

Version history: (Expand)