./cad/gplcver, Verilog simulator

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Branch: pkgsrc-2009Q4, Version: 2.11a, Package name: gplcver-2.11a, Maintainer: pkgsrc-users

Cver is a full 1995 IEEE P1364 standard Verilog simulator. It also
implements some of the 2001 P1364 standard features. All three
PLI interfaces (tf_, acc_, and vpi_) are implemented as defined
in the IEEE 2001 P1364 LRM.

Master sites:

SHA1: 5b26b70282bb7c79f5dfa9d70f3cf0972ac03b3c
RMD160: 16bedab414af0cf4049394ea9f01ea2ebb4e3385
Filesize: 1161.562 KB

Version history: (Expand)