./cad/MyHDL-iverilog, Icarus Verilog cosimulation support for py-MyHDL

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Branch: pkgsrc-2017Q1, Version: 0.9.0, Package name: MyHDL-iverilog-0.9.0, Maintainer: pkgsrc-users

MyHDL is a Python package for using Python as a hardware
description language. Popular hardware description languages, like
Verilog and VHDL, are compiled languages. MyHDL with Python
can be viewed as a "scripting language" counterpart of such
languages. However, Python is more accurately described as a very
high level language (VHLL). MyHDL users have access to the
amazing power and elegance of Python for their modeling work.


Required to build:
[devel/gperf]

Master sites:

SHA1: 90ee6ab6983d4c11a30a6cca5c749e4affdd8ff1
RMD160: 1aac0472829b8a3b171364ed3c85fd9e87a41537
Filesize: 452.186 KB

Version history: (Expand)