./cad/verilator, Verilog HDL simulator

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Branch: pkgsrc-2018Q4, Version: 4.006, Package name: verilator-4.006, Maintainer: ryoon

Verilator is the fastest free Verilog HDL simulator, and outperforms
most commercial simulators. Verilator compiles synthesizable
SystemVerilog (generally not test-bench code), plus some SystemVerilog
and Synthesis assertions into single- or multithreaded C++ or
SystemC code. Verilator is designed for large projects where fast
simulation performance is of primary concern, and is especially
well suited to generate executable models of CPUs for embedded
software design teams.


Required to build:
[devel/flex]

Master sites:

SHA1: f731c8c8b4b366d806e6a80a52d0b23a5528a054
RMD160: 541a370ceb99a012837ced786bff104510533101
Filesize: 2451.254 KB

Version history: (Expand)