./cad/verilator, Verilog HDL simulator

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Branch: pkgsrc-2019Q2, Version: 4.012, Package name: verilator-4.012, Maintainer: ryoon

Verilator is the fastest free Verilog HDL simulator, and outperforms
most commercial simulators. Verilator compiles synthesizable
SystemVerilog (generally not test-bench code), plus some SystemVerilog
and Synthesis assertions into single- or multithreaded C++ or
SystemC code. Verilator is designed for large projects where fast
simulation performance is of primary concern, and is especially
well suited to generate executable models of CPUs for embedded
software design teams.


Required to build:
[pkgtools/cwrappers] [devel/flex]

Master sites:

SHA1: 653688c0dc8521d8d3ab9f9e94180f2271ec08ff
RMD160: d15a54b8243caf5e22c3f9c6f6ff76ee7a37219b
Filesize: 2454.403 KB

Version history: (Expand)