./cad/py-MyHDL, Hardware description in Python

[ CVSweb ] [ Homepage ] [ RSS ] [ Required by ] [ Add to tracker ]

Branch: pkgsrc-2019Q3, Version: 0.10nb1, Package name: py37-MyHDL-0.10nb1, Maintainer: pkgsrc-users

MyHDL is a Python package for using Python as a hardware
description language. Popular hardware description languages, like
Verilog and VHDL, are compiled languages. MyHDL with Python
can be viewed as a "scripting language" counterpart of such
languages. However, Python is more accurately described as a very
high level language (VHLL). MyHDL users have access to the
amazing power and elegance of Python for their modeling work.

Required to build:

Master sites:

SHA1: d766a1a556e9dce23af07d1b378fbcc6e3b86494
RMD160: 234d3f3c5d2d84e548e317e1b85bc28efbfd7b14
Filesize: 1177.213 KB

Version history: (Expand)