./cad/verilator, Verilog HDL simulator

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Branch: pkgsrc-2019Q3, Version: 4.016, Package name: verilator-4.016, Maintainer: ryoon

Verilator is the fastest free Verilog HDL simulator, and outperforms
most commercial simulators. Verilator compiles synthesizable
SystemVerilog (generally not test-bench code), plus some SystemVerilog
and Synthesis assertions into single- or multithreaded C++ or
SystemC code. Verilator is designed for large projects where fast
simulation performance is of primary concern, and is especially
well suited to generate executable models of CPUs for embedded
software design teams.

Required to build:

Master sites:

SHA1: dce30a001574e743198179e4f95939d84b69c7f8
RMD160: eba0e31b5b4a9769fb65b842c9a4b9d4b34ecfb6
Filesize: 2477.001 KB

Version history: (Expand)