./cad/gplcver, Verilog simulator

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Branch: pkgsrc-2021Q1, Version: 2.12a, Package name: gplcver-2.12a, Maintainer: pkgsrc-users

Cver is a full 1995 IEEE P1364 standard Verilog simulator. It also
implements some of the 2001 P1364 standard features. All three
PLI interfaces (tf_, acc_, and vpi_) are implemented as defined
in the IEEE 2001 P1364 LRM.

Master sites:

SHA1: 946bb35b6279646c6e10c309922ed17deb2aca8a
RMD160: 5af004b345142ac5400c9defc7125bbe127d2c49
Filesize: 1195.771 KB

Version history: (Expand)