./cad/covered, Verilog code coverage analyzer (stable release version)

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Branch: pkgsrc-2021Q3, Version: 0.7.10nb2, Package name: covered-0.7.10nb2, Maintainer: dmcmahill

Covered is a Verilog code coverage analysis tool that can be useful
for determining how well a diagnostic test suite is covering the
design under test. Typically in the design verification work flow, a
design verification engineer will develop a self-checking test suite
to verify design elements/functions specified by a design's
specification document. When the test suite contains all of the tests
required by the design specification, the test writer may be asking
him/herself, "How much logic in the design is actually being
exercised?", "Does my test suite cover all of the logic under test?",
and "Am I done writing tests for the logic?". When the design
verification gets to this point, it is often useful to get some
metrics for determining logic coverage. This is where a code coverage
utility, such as Covered, is very useful.

Please note that this package is for a stable release version.
There is a separate package (covered-current) which is made of
development snapshots.

Master sites:

SHA1: 3f7f27ccb9d9263a27f5c8ae97e5569bf434c2f2
RMD160: 9e9146753aa542663fc43924d64601e8f16be316
Filesize: 3035.413 KB

Version history: (Expand)