./cad/verilator, Verilog HDL simulator

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Branch: pkgsrc-2021Q3, Version: 4.100nb1, Package name: verilator-4.100nb1, Maintainer: ryoon

Verilator is the fastest free Verilog HDL simulator, and outperforms
most commercial simulators. Verilator compiles synthesizable
SystemVerilog (generally not test-bench code), plus some SystemVerilog
and Synthesis assertions into single- or multithreaded C++ or
SystemC code. Verilator is designed for large projects where fast
simulation performance is of primary concern, and is especially
well suited to generate executable models of CPUs for embedded
software design teams.

Master sites:

SHA1: 8e241f91d831d8b6d6f4a263e7f00078dcf990c4
RMD160: b23304d3e9550d6e32f851c6e98a4e523787e342
Filesize: 2682.754 KB

Version history: (Expand)