Log message:
Recursive ABI depends update and PKGREVISION bump for readline-6.0 shlib
major change.

Reported by Robert Elz in PR 41345.

Log message:
Simply and speed up buildlink3.mk files and processing.
This changes the buildlink3.mk files to use an include guard for the
recursive include. The use of BUILDLINK_DEPTH, BUILDLINK_DEPENDS,
BUILDLINK_PACKAGES and BUILDLINK_ORDER is handled by a single new
variable BUILDLINK_TREE. Each buildlink3.mk file adds a pair of
enter/exit marker, which can be used to reconstruct the tree and
to determine first level includes. Avoiding := for large variables
(BUILDLINK_ORDER) speeds up parse time as += has linear complexity.
The include guard reduces system time by avoiding reading files over and
over again. For complex packages this reduces both %user and %sys time to
half of the former time.

Log message:
update to verilog-0.8.7, the latest in the stable 0.8 series.

Release Notes for Icarus Verilog 0.8.7

none (but see below for other releases since the last version in pkgsrc)

Release Notes for Icarus Verilog 0.8.6

This is a bug fix update of the 0.8 stable version of Icarus
Verilog. The v0.8 series tries to remain as stable as possible while
still fixing bugs that are safe to fix.

Preprocessor:

* Fix parse/preprocess of C-style comments in surpressed ifdef
  blocks.

* Support leading underscore in preprocessor names.

Compilation/elaboration issues:

* Support min:typ:max expressions in more places.

* Fix handling of @* non-input nets.

* Do not support system functions in continuous assignments.
* Do not support converting vectors to real.
* Do not support constant real valued expressions.

Run-time ussues:

* Fix comparison of negative numbers that happen to be equal.

* Fix bad execution of certain expressions caused by code generator
  bad lookaside handling.

* Proper error message for invalid bit selects.

* Implement $printtimescale system task.

Compiler build issues:

* Compile OK evel if libbzip2 is not installed, but do not support
  LXT2 in that case.

Release Notes for Icarus Verilog 0.8.5

This is mostly a bug-fix release for the 0.8 stable branch.

* Fix assertions from unary operators with certain operand widths.

* Fix incorrect comparison results when in certain cases comparing two
signed negative integers.

* Latch synthesis has been added to the core synthesizer

* Add nand gate support to the edif code generator

* Minor compile time errors/warnings
* Improved messages from the configure script

Release Notes for Icarus Verilog 0.8.4

This is a bug-fix release for the 0.8 stable branch. The 0.8 stable
branch updates do not include significant new features (they go into
the devel branch instead) nor fixes that are deemed to drastic to
include in a stable tool.

- Various source code portability problems have been fixed. The 0.8 no
  longer compiles on many modern systems.

- Various bug reports have been put to rest with this release. Some
  parser errors have been fixed (including a few regressions from
  0.8.3) and a few new syntaxes added.

- A variety of systhesis bug fixes and enhancements are included in
  0.8.4. Currently, synthesis is only actively supported in the 0.8
  branch, and the 0.8.4 is the most complete.

Log message:
Don't use malloc.h.

Log message:
update to verilog-0.8.3

** Release Notes for Icarus Verilog 0.8.3

This is a new release of the stable 0.8 branch. The changes from 0.8.2
are intended to be evolutionary, rather then revolutionary, to enhance
the stability of the branch.

Various simulator bugs have been fixed, including (but not limited to):
- Detect overrun of timescale vs. precision
- Handle more operators in constant expressions
- Various ivl crashes and panics fixed.
- Some performance bottlenecks have been fixed.
- Various tool compilation problems have been fixed.

Also, the internal synthesizer (for synthesis targets) has been
considerably improved. NOTE that the code generators have not been
improved to take advantage of all the changes here, so there is work
yet to be done.

The mingw build process for compiling in Windows has been reworked. It
is now possible (indeed preferable) to compile fully native Icarus
Verilog binaries on Windows with no Cygwin tools at all.

Log message:
Change the format of BUILDLINK_ORDER to contain depth information as well,
and add a new helper target and script, "show-buildlink3", that outputs
a listing of the buildlink3.mk files included as well as the depth at
which they are included.

For example, "make show-buildlink3" in fonts/Xft2 displays:

	zlib
	fontconfig
	    iconv
	    zlib
	    freetype2
	    expat
	freetype2
	Xrender
	    renderproto

Log message:
Track information in a new variable BUILDLINK_ORDER that informs us
of the order in which buildlink3.mk files are (recursively) included
by a package Makefile.

Log message:
For building verilog, lex is indeed needed.

Log message:
Needs bison.

Log message:
Fixed pkglint warnings. Since bison and lex are not used when building,
they don't need to be defined in USE_TOOLS.