Log message:
replace deprecated USE_GMAKE with USE_GNU_TOOLS+=make.

Log message:
Update to covered-0.2.2.

>From the NEWS file:

This release is basically a 0.2.1 release with the available bug fixes
patches applied to it.  This should make getting a stable release less
tedious.

Log message:
Fix REPLACE_PERL: pathnames listed should be relative to ${WRKSRC}.

Log message:
Regen with file as sourceforge shows it.

Log message:
import covered-0.2.1

Covered is a Verilog code coverage analysis tool that can be useful
for determining how well a diagnostic test suite is covering the
design under test. Typically in the design verification work flow, a
design verification engineer will develop a self-checking test suite
to verify design elements/functions specified by a design's
specification document. When the test suite contains all of the tests
required by the design specification, the test writer may be asking
him/herself, "How much logic in the design is actually being
exercised?", "Does my test suite cover all of the logic under test?",
and "Am I done writing tests for the logic?".  When the design
verification gets to this point, it is often useful to get some
metrics for determining logic coverage. This is where a code coverage
utility, such as Covered, is very useful.

Please note that this package is for a stable release version.
There is a seperate package (covered-current) which is made of
development snapshots.