Subject: CVS commit: pkgsrc/cad/verilog
From: Dan McMahill
Date: 2002-12-15 02:57:12
Message id: 20021215015712.7B160B42C@cvs.netbsd.org
Log Message:
update to verilog-0.7

This release represents many bug fixes, expanded language coverage,
greatly enhanced xilinx fpga synthesis and several performance enhancements.
The complete list is rather long.
Files:
RevisionActionfile
1.13modifypkgsrc/cad/verilog/Makefile
1.3modifypkgsrc/cad/verilog/PLIST
1.5modifypkgsrc/cad/verilog/distinfo