Subject: CVS commit: pkgsrc/cad/verilog-current
From: Matthias Drochner
Date: 2003-07-14 11:51:49
Message id: 20030714095150.463A4B004@cvs.netbsd.org

Log Message:
update to snapshot "20030705".
There was a couple of snapshots since february; besides bugfixes the
major highligths might be:
-handling of real values at various places
-support for library modules (esp cadence PLI1)
-better FPGA support (esp Virtex II)
-"vvp" interactive mode added

Also converted to buildlink2, and dependencies to libz, libbz2 and
readline added.

Files:
RevisionActionfile
1.33modifypkgsrc/cad/verilog-current/Makefile
1.5modifypkgsrc/cad/verilog-current/PLIST
1.17modifypkgsrc/cad/verilog-current/distinfo
1.12modifypkgsrc/cad/verilog-current/patches/patch-ad