Subject: CVS commit: pkgsrc/cad/verilog-current
From: Matthias Drochner
Date: 2003-08-25 13:21:51
Message id: 20030825112152.410A9B004@cvs.netbsd.org
Log Message:
update to the 20030815 shapshot
changes are basically bugfixes, and improvements in the FPGA synthesis
area
Files:
RevisionActionfile
1.35modifypkgsrc/cad/verilog-current/Makefile
1.18modifypkgsrc/cad/verilog-current/distinfo