Subject: CVS commit: pkgsrc/cad/py-MyHDL
From: Matthias Drochner
Date: 2005-01-05 16:20:10
Message id: 20050105152010.C308C2DA1D@cvs.netbsd.org
Log Message:
update to 0.4.1
changes:
* VCD output for waveform viewing
- function additions
- needs Python 2.3, 2.4 is OK
* Conversion to Verilog to provide a path to implementation
* Added cosimulation support for the cver Verilog simulator.
- bugfixes
Files:
RevisionActionfile
1.7modifypkgsrc/cad/py-MyHDL/Makefile
1.3modifypkgsrc/cad/py-MyHDL/PLIST
1.2modifypkgsrc/cad/py-MyHDL/distinfo