Subject: CVS commit: pkgsrc/cad/py-MyHDL
From: Matthias Drochner
Date: 2006-02-10 17:06:46
Message id: 20060210160646.AD3842DA27@cvs.netbsd.org

Log Message:
update to 0.5
major changes:
-supports Python decorator syntax for generators (needs 2.4)
-intbv() doesn't have a default anymore
-many improvements to Verilog conversion

Files:
RevisionActionfile
1.11modifypkgsrc/cad/py-MyHDL/Makefile
1.4modifypkgsrc/cad/py-MyHDL/PLIST
1.4modifypkgsrc/cad/py-MyHDL/distinfo