Subject: CVS commit: pkgsrc/cad/MyHDL-iverilog
From: Matthias Drochner
Date: 2006-02-10 18:05:03
Message id: 20060210170503.1580F2DA27@cvs.netbsd.org
Log Message:
import MyHDL-iverilog-0.5, an Icarus Verilog vpi module to support cosimulation
from py-MyHDL
Files:
RevisionActionfile
1.1importpkgsrc/cad/MyHDL-iverilog/Makefile
1.1importpkgsrc/cad/MyHDL-iverilog/DESCR
1.1importpkgsrc/cad/MyHDL-iverilog/distinfo
1.1importpkgsrc/cad/MyHDL-iverilog/PLIST