Subject: CVS commit: pkgsrc/cad
From: Matthias Drochner
Date: 2006-05-04 18:58:05
Message id: 20060504165805.6EEE22DA27@cvs.netbsd.org

Log Message:
update MyHDL to 0.5.1
There is no usable changelog; I've found one real bug closed in the
tracker: A verilog '>>>' is generated as appropriate for signed numbers.

Files:
RevisionActionfile
1.3modifypkgsrc/cad/MyHDL-gplcver/Makefile
1.2modifypkgsrc/cad/MyHDL-gplcver/distinfo
1.2modifypkgsrc/cad/MyHDL-gplcver/patches/patch-aa
1.3modifypkgsrc/cad/MyHDL-iverilog/Makefile
1.2modifypkgsrc/cad/MyHDL-iverilog/distinfo
1.13modifypkgsrc/cad/py-MyHDL/Makefile
1.5modifypkgsrc/cad/py-MyHDL/PLIST
1.5modifypkgsrc/cad/py-MyHDL/distinfo