Subject: CVS commit: pkgsrc/cad/verilog
From: Dan McMahill
Date: 2006-05-06 21:13:55
Message id: 20060506191355.D03002DA27@cvs.netbsd.org
Log Message:
update to verilog-0.8.2.  Adds edif output, contains several bug fixes for
compatibility with more c++ compilers.
Files:
RevisionActionfile
1.26modifypkgsrc/cad/verilog/Makefile
1.5modifypkgsrc/cad/verilog/PLIST
1.10modifypkgsrc/cad/verilog/distinfo