Log Message: initial import of verilog-mode-3.60 This is a major mode for editing Verilog HDL source code under GNU Emacs or XEmacs.
Revision | Action | file |
1.1 | import | pkgsrc/cad/verilog-mode/distinfo |
1.1 | import | pkgsrc/cad/verilog-mode/PLIST |
1.1 | import | pkgsrc/cad/verilog-mode/Makefile |
1.1 | import | pkgsrc/cad/verilog-mode/MESSAGE |
1.1 | import | pkgsrc/cad/verilog-mode/DESCR |