Log Message: update to verilog-0.7 This release represents many bug fixes, expanded language coverage, greatly enhanced xilinx fpga synthesis and several performance enhancements. The complete list is rather long.
Revision | Action | file |
1.13 | modify | pkgsrc/cad/verilog/Makefile |
1.3 | modify | pkgsrc/cad/verilog/PLIST |
1.5 | modify | pkgsrc/cad/verilog/distinfo |