Log Message:
update to verilog-0.8.3

** Release Notes for Icarus Verilog 0.8.3

This is a new release of the stable 0.8 branch. The changes from 0.8.2
are intended to be evolutionary, rather then revolutionary, to enhance
the stability of the branch.

Various simulator bugs have been fixed, including (but not limited to):
- Detect overrun of timescale vs. precision
- Handle more operators in constant expressions
- Various ivl crashes and panics fixed.
- Some performance bottlenecks have been fixed.
- Various tool compilation problems have been fixed.

Also, the internal synthesizer (for synthesis targets) has been
considerably improved. NOTE that the code generators have not been
improved to take advantage of all the changes here, so there is work
yet to be done.

The mingw build process for compiling in Windows has been reworked. It
is now possible (indeed preferable) to compile fully native Icarus
Verilog binaries on Windows with no Cygwin tools at all.