Subject: CVS commit: pkgsrc/cad/verilog-current
From: Dan McMahill
Date: 2007-03-01 02:03:45
Message id: 20070301010346.185A52150A@cvs.netbsd.org

Log Message:
update to verilog-current-20070227

Release Notes for Icarus Verilog Snapshot 20070227

* Fix some problems with specify block parsing. Detect some cases that
  are parsed but not properly implemented yet and issue warnings or
  errors. Also fixed a few problems with inertial delay model timing.

* Detect is some cases Verilog source errors that can be better
  reported to users. This includes more specific error messages for
  certain syntax errors.

* Fix problems with overridden continuous assignments.

* Hide bool types from logic type as far as VPI is concerned, for the
  sake of compatibility.

* Fix a variety of code generator expression lifetime bugs that caused
  obscure (and wrong) output results in behavioral code.

* iverilog-vpi uses the compiler selected at build time.

* Rework handling of strings to handle escape sequences properly.

* Fix some handling of real values in some expression types.

* Get padding of sized, unsigned numbers when x or z are involved.

* Many, many more misc. bug fixes.

* Add an assert mechinism that improves usefulness of bug reports by
  reporting source file line numbers when available.

* Compile fixes, using inttypes.h instead of stdint for portability.

* Various spelling fixes.

Files:
RevisionActionfile
1.55modifypkgsrc/cad/verilog-current/Makefile
1.29modifypkgsrc/cad/verilog-current/distinfo