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./wip/verilog-current, Verilog simulation and synthesis tool (development snapshot version)

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Branch: CURRENT, Version: 20150105, Package name: verilog-current-20150105, Maintainer: dmcmahill

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
compiler, compiling source code writen in Verilog (IEEE-1364) into some target
format. For batch simulation, the compiler can generate C++ code that is
compiled and linked with a run time library (called "vvm") then executed as
a command to run the simulation. For synthesis, the compiler generates
netlists in the desired format.

The compiler proper is intended to parse and elaborate design descriptions
written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
complex standard, so it will take some time for it to get there, but that's
the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well,
and some -1999 features will creep in.

Please note that this package is a development snapshot and while it contains
the latest and greatest features, it may be buggy as well. There is a separate
verilog package which is made of the stable releases.


Required to build:
[devel/gperf]

Master sites:

SHA1: be40492878f2597659ff0165d1dd72c0cfd5ab38
RMD160: d05cee4ade030fe3583c9edbdef923537fc94ce8
Filesize: 1621.648 KB

Version history: (Expand)

CVS history: (Expand)


   2015-04-01 04:50:44 by Makoto Fujiwara | Files touched by this commit (1) 
Log message:
(1) Sort list of files on SUBST_FILES.dep (2) Remove duplication from those
   2015-04-01 04:40:52 by Makoto Fujiwara | Files touched by this commit (2) 
Log message:
(upstream)
 - Update to 2015/01/05, ChangeLog, Release note not found
(pkgsrc)
 - Correction to SUBST_SED.dep. Had two problem, pkglint, and wrong edit string
   2014-12-29 11:56:18 by Makoto Fujiwara | Files touched by this commit (3) 
Log message:
Re: [Iverilog-devel] More vec4-stack progress
From: Stephen Williams <steve@ic...> - 2014-12-05 22:05:48
      ....
OK, that's very useful feedback. Given that, and assuming no other
complaints, I will merge the vec4-stack branch into git master tomorrow,
Saturday, 6 Dec. in the morning.

In the mean time, I've made a 20141205 snapshot available in the
usual FTP download site. That is the last snapshot before the big
merge.
      ....
   2014-10-09 16:06:26 by Thomas Klausner | Files touched by this commit (97) 
Log message:
Remove pkgviews: don't set PKG_INSTALLATION_TYPES in Makefiles.
   2014-02-15 14:40:19 by Makoto Fujiwara | Files touched by this commit (1) 
Log message:
Update HOMEPAGE.
   2013-12-20 16:27:35 by Makoto Fujiwara | Files touched by this commit (1) 
Log message:
dep directory should be made before compile.
   2013-12-20 07:09:41 by Makoto Fujiwara | Files touched by this commit (3) 
Log message:
(1) Add several install files under post-install: target.
This keeps PLIST as before. But this solution may be neatly
replaced smaller line patch  (Not dugged yet).
(2) MAKE_JOBS didn't seem to be safe, so add minor patch
for vip/Makefile.in to dependency on dep directory.
   2013-12-20 03:19:53 by Makoto Fujiwara | Files touched by this commit (7) 
Log message:
Import verilog-current-20130827 as wip/verilog-current.

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
compiler, compiling source code writen in Verilog (IEEE-1364) into some target
format. For batch simulation, the compiler can generate C++ code that is
compiled and linked with a run time library (called "vvm") then executed as
a command to run the simulation. For synthesis, the compiler generates
netlists in the desired format.

The compiler proper is intended to parse and elaborate design descriptions
written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
complex standard, so it will take some time for it to get there, but that's
the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well,
and some -1999 features will creep in.

Please note that this package is a development snapshot and while it contains
the latest and greatest features, it may be buggy as well.  There is a separate
verilog package which is made of the stable releases.