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./wip/iverilog, Verilog simulation and synthesis tool

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Branch: CURRENT, Version: 10.1, Package name: iverilog-10.1, Maintainer: pkgsrc-users

Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard.


Required to build:
[devel/gperf]

Master sites:

SHA1: 5aeabe8553bd42d5788f4ebba995c37b4bd966bc
RMD160: 90ae1db06dc309ce7afb94f75434e57c58a02596
Filesize: 1548.988 KB

Version history: (Expand)