NOTICE: This package has been removed from pkgsrc

./wip/iverilog, Verilog simulation and synthesis tool (stable release version)

[ CVSweb ] [ Homepage ] [ RSS ] [ Required by ]

Branch: CURRENT, Version: 12.0, Package name: iverilog-12.0, Maintainer: dmcmahill

Icarus Verilog is intended to compile ALL of the Verilog HDL as described in
the IEEE-1364 standard. Of course, it's not quite there yet. It does currently
handle a mix of structural and behavioral constructs.

Icarus Verilog is not aimed at being a simulator in the traditional sense, but
a compiler that generates code employed by back-end tools.


Required to build:
[devel/gperf]

Master sites:

Filesize: 2924.898 KB

Version history: (Expand)