./wip/verilator, Free and fast Verilog HDL simulator

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Branch: CURRENT, Version: 3.886, Package name: verilator-3.886, Maintainer: pkgsrc-users

Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus some
PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs for
embedded software design teams.

Required to run:

Required to build:

Master sites:

SHA1: d50e4ef59f318082f7a8aadb6e423db27e733135
RMD160: a2f6d64d4fbdcec94634d8470e181ad3a4dddb2e
Filesize: 1960.197 KB

Version history: (Expand)