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wip/verilator,
Convert HDL (Verilog etc) into a C++ or SystemC model
Branch: CURRENT,
Version: 5.026,
Package name: verilator-5.026,
Maintainer: pkgsrc-usersVerilator is the fastest free Verilog HDL simulator, and outperforms
most commercial simulators. Verilator compiles synthesizable
SystemVerilog (generally not test-bench code), plus some SystemVerilog
and Synthesis assertions into single- or multithreaded C++ or
SystemC code. Verilator is designed for large projects where fast
simulation performance is of primary concern, and is especially
well suited to generate executable models of CPUs for embedded
software design teams.
Required to run:[
devel/p5-Getopt-Long]
Required to build:[
pkgtools/cwrappers]
Master sites:
Filesize: 3839.255 KB
Version history: (Expand)
- (2024-07-13) Package has been reborn
- (2024-07-13) Updated to version: verilator-5.026
- (2019-08-26) Package deleted from pkgsrc
- (2019-08-22) Updated to version: verilator-4.016
- (2019-06-25) Package has been reborn
- (2019-06-11) Package deleted from pkgsrc