./cad/verilog, Verilog simulation and synthesis tool (stable release version)

[ CVSweb ] [ Homepage ] [ RSS ] [ Required by ] [ Add to tracker ]

Branch: pkgsrc-2009Q1, Version: 0.8.7, Package name: verilog-0.8.7, Maintainer: dmcmahill

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
compiler, compiling source code writen in Verilog (IEEE-1364) into some target
format. For batch simulation, the compiler can generate C++ code that is
compiled and linked with a run time library (called "vvm") then executed as
a command to run the simulation. For synthesis, the compiler generates
netlists in the desired format.

The compiler proper is intended to parse and elaborate design descriptions
written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
complex standard, so it will take some time for it to get there, but that's
the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well,
and some -1999 features will creep in.


Required to build:
[devel/gmake] [devel/bison] [devel/gperf]

Master sites:

SHA1: 814f12a99463a637cb13e0d86755f762c5d90270
RMD160: 63fb4f9e1e85157010d480e5d66513d6c9ac4326
Filesize: 1244.113 KB

Version history: (Expand)