./cad/covered-current, Verilog code coverage analyzer (development snapshot)

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Branch: pkgsrc-2010Q1, Version: 20060904, Package name: covered-current-20060904, Maintainer: dmcmahill

Covered is a Verilog code coverage analysis tool that can be useful
for determining how well a diagnostic test suite is covering the
design under test. Typically in the design verification work flow, a
design verification engineer will develop a self-checking test suite
to verify design elements/functions specified by a design's
specification document. When the test suite contains all of the tests
required by the design specification, the test writer may be asking
him/herself, "How much logic in the design is actually being
exercised?", "Does my test suite cover all of the logic under test?",
and "Am I done writing tests for the logic?". When the design
verification gets to this point, it is often useful to get some
metrics for determining logic coverage. This is where a code coverage
utility, such as Covered, is very useful.

Please note that this package is a development snapshot and while it
contains the latest and greatest features, it may be buggy as well.
There is a separate package which is made of the stable releases.


Required to run:
[cad/verilog]

Master sites:

SHA1: 78869b20bc6e032b4dac3a3029c4ea6a97962d3a
RMD160: c1a9e841f7e0a341bd8bce5c4f04e349e0b07672
Filesize: 1512.83 KB

Version history: (Expand)