NOTICE: This package has been removed from pkgsrc

./cad/verilog, Verilog simulation and synthesis tool (stable release version)

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Branch: CURRENT, Version: 0.9.7, Package name: verilog-0.9.7, Maintainer: dmcmahill

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
compiler, compiling source code writen in Verilog (IEEE-1364) into some target
format. For batch simulation, the compiler can generate C++ code that is
compiled and linked with a run time library (called "vvm") then executed as
a command to run the simulation. For synthesis, the compiler generates
netlists in the desired format.

The compiler proper is intended to parse and elaborate design descriptions
written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
complex standard, so it will take some time for it to get there, but that's
the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well,
and some -1999 features will creep in.

Master sites:

SHA1: 714c2a605779957490cca24e3dc01d096dbc1474
RMD160: 3bac03ca703465a43c5a0a8175a3d27ee00f49a7
Filesize: 1209.07 KB

Version history: (Expand)

CVS history: (Expand)

   2016-10-09 01:15:53 by Kamil Rytarowski | Files touched by this commit (8) | Package removed
Log message:
cad/verilog has been renamed to cad/iverilog

Use saner and more specific name for this package.

No objection for rename from <gdt>
   2016-10-09 00:30:43 by Kamil Rytarowski | Files touched by this commit (6)
Log message:
Update cad/verilog (icarus verilog) from 0.9.7 to 10.1.1

pkgsrc changes:
 - note GitHub tags (but not use them for now)
 - remove conflict with nonexistent verilog-current
 - install additional documentation in share/doc/ivl (not share/ivl)
 - drop DESTDIR gymnastics - build works without it
 - (re)enable gperf dependency
 - regenerate
 - drop patches/ - no longer needed
 - patches/patch-vpi_Makefile partially fixed upstream - rest not needed

upstream changelog

Probably the only notes available:

Here are the release notes for Icarus Verilog release branch 10. The 10
release is a huge improvement over the 0.9 release series, in every
aspect. Much more of the Verilog and SystemVerilog language is supported,
many bugs have been fixed, and performance has improved. The changes
(improvements!) are so numerous that there is no point attempting to
enumerate them.

   2016-07-25 01:43:12 by Roland Illig | Files touched by this commit (1)
Log message:
Fixed pkglint warnings about unknown sed commands.
   2016-06-01 15:30:41 by Joerg Sonnenberger | Files touched by this commit (1)
Log message:
Force creation of dep directories to prevent race conditions during the
actual build.
   2015-11-03 01:21:20 by Alistair G. Crooks | Files touched by this commit (58)
Log message:
Add SHA512 digests for distfiles for cad category

Problems found with existing distfile for eagle:
No changes made to eagle/distinfo file.

Otherwise, existing SHA1 digests verified and found to be the same on
the machine holding the existing distfiles (morden).  All existing
SHA1 digests retained for now as an audit trail.
   2015-02-18 21:12:02 by Joerg Sonnenberger | Files touched by this commit (2)
Log message:
Fix race condition.
   2014-10-09 16:07:17 by Thomas Klausner | Files touched by this commit (1163)
Log message:
Remove pkgviews: don't set PKG_INSTALLATION_TYPES in Makefiles.
   2014-06-28 23:05:11 by David A. Holland | Files touched by this commit (3)
Log message:
Work around build problem seen only in pbulk (remains unclear why).

Disable build dependence on gperf as the build doesn't actually run
it, and also for this workaround I need to patch the gperf output