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cad/MyHDL-iverilog,
Icarus Verilog cosimulation support for py-MyHDL
Branch: pkgsrc-2014Q1,
Version: 0.7,
Package name: MyHDL-iverilog-0.7,
Maintainer: pkgsrc-usersMyHDL is a Python package for using Python as a hardware
description language. Popular hardware description languages, like
Verilog and VHDL, are compiled languages. MyHDL with Python
can be viewed as a "scripting language" counterpart of such
languages. However, Python is more accurately described as a very
high level language (VHLL). MyHDL users have access to the
amazing power and elegance of Python for their modeling work.
Required to run:[
cad/verilog]
Required to build:[
devel/gperf]
Master sites:
SHA1: 4382444230297593f0a08ba8178c542b4ce1f19b
RMD160: c525b21a86c9204ec7cf659709bc0e8fb2c7450b
Filesize: 236.104 KB
Version history: (Expand)
- (2014-04-04) Package has been reborn
- (2014-04-03) Package added to pkgsrc.se, version MyHDL-iverilog-0.7 (created)