./cad/verilog-current, Verilog simulation and synthesis tool (development snapshot version)

[ CVSweb ] [ Homepage ] [ RSS ] [ Required by ] [ Add to tracker ]

Branch: pkgsrc-2014Q2, Version: 20090923nb1, Package name: verilog-current-20090923nb1, Maintainer: dmcmahill

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
compiler, compiling source code writen in Verilog (IEEE-1364) into some target
format. For batch simulation, the compiler can generate C++ code that is
compiled and linked with a run time library (called "vvm") then executed as
a command to run the simulation. For synthesis, the compiler generates
netlists in the desired format.

The compiler proper is intended to parse and elaborate design descriptions
written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
complex standard, so it will take some time for it to get there, but that's
the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well,
and some -1999 features will creep in.

Please note that this package is a development snapshot and while it contains
the latest and greatest features, it may be buggy as well. There is a separate
verilog package which is made of the stable releases.

Required to build:

Master sites:

SHA1: 1836ebc4ef78341fb1a077e807c8d5b195ebb253
RMD160: 32a009d1390e71721d3a72a1940b655ed1853ba5
Filesize: 1095.094 KB

Version history: (Expand)