./cad/verilog, Verilog simulation and synthesis tool (stable release version)

[ CVSweb ] [ Homepage ] [ RSS ] [ Required by ] [ Add to tracker ]

Branch: pkgsrc-2015Q1, Version: 0.9.7, Package name: verilog-0.9.7, Maintainer: dmcmahill

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
compiler, compiling source code writen in Verilog (IEEE-1364) into some target
format. For batch simulation, the compiler can generate C++ code that is
compiled and linked with a run time library (called "vvm") then executed as
a command to run the simulation. For synthesis, the compiler generates
netlists in the desired format.

The compiler proper is intended to parse and elaborate design descriptions
written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
complex standard, so it will take some time for it to get there, but that's
the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well,
and some -1999 features will creep in.

Master sites:

SHA1: 714c2a605779957490cca24e3dc01d096dbc1474
RMD160: 3bac03ca703465a43c5a0a8175a3d27ee00f49a7
Filesize: 1209.07 KB

Version history: (Expand)