./cad/verilator, Verilog HDL simulator

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Branch: pkgsrc-2020Q1, Version: 4.030, Package name: verilator-4.030, Maintainer: ryoon

Verilator is the fastest free Verilog HDL simulator, and outperforms
most commercial simulators. Verilator compiles synthesizable
SystemVerilog (generally not test-bench code), plus some SystemVerilog
and Synthesis assertions into single- or multithreaded C++ or
SystemC code. Verilator is designed for large projects where fast
simulation performance is of primary concern, and is especially
well suited to generate executable models of CPUs for embedded
software design teams.


Required to build:
[devel/flex]

Master sites:

SHA1: 6f70b648a2962ba52b31dd46684b7fad20cbd9c4
RMD160: 36f50f095926f88dc3859ea6504fb07593f928ec
Filesize: 2437.699 KB

Version history: (Expand)