./cad/iverilog, Verilog simulation and synthesis tool (stable release version)

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Branch: CURRENT, Version: 12.0, Package name: iverilog-12.0, Maintainer: dmcmahill

Icarus Verilog is intended to compile ALL of the Verilog HDL as described in
the IEEE-1364 standard. Of course, it's not quite there yet. It does currently
handle a mix of structural and behavioral constructs.

Icarus Verilog is not aimed at being a simulator in the traditional sense, but
a compiler that generates code employed by back-end tools.


Required to build:
[devel/gperf] [pkgtools/cwrappers]

Master sites:

Filesize: 2924.898 KB

Version history: (Expand)

CVS history: (Expand)


   2021-10-26 12:04:17 by Nia Alarie | Files touched by this commit (63) 
Log message:
cad: Replace RMD160 checksums with BLAKE2s checksums

All checksums have been double-checked against existing RMD160 and
SHA512 hashes
   2021-10-07 15:20:33 by Nia Alarie | Files touched by this commit (63) 
Log message:
cad: Remove SHA1 hashes for distfiles
   2020-09-27 15:48:21 by Makoto Fujiwara | Files touched by this commit (2) 
Log message:
(cad/iverilog) Fix build, adapting to bison 3.7.1
   2020-03-26 03:37:14 by Joerg Sonnenberger | Files touched by this commit (8) 
Log message:
Fix racy bison use. Rename patch to match patched file.
   2020-02-18 18:44:26 by Joerg Sonnenberger | Files touched by this commit (2) 
Log message:
Revert intentional commit.
   2018-01-07 14:04:44 by Roland Illig | Files touched by this commit (583) 
Log message:
Fix indentation in buildlink3.mk files.

The actual fix as been done by "pkglint -F */*/buildlink3.mk", and was
reviewed manually.

There are some .include lines that still are indented with zero spaces
although the surrounding .if is indented. This is existing practice.
   2016-10-09 01:01:46 by Kamil Rytarowski | Files touched by this commit (8) 
Log message:
Import iverilog (Icarus Verilog) 10.1.1 as cad/iverilog

It's a rename of cad/verilog to a better name.

Updated DESCR for new package:

Icarus Verilog is intended to compile ALL of the Verilog HDL as described in
the IEEE-1364 standard. Of course, it's not quite there yet. It does currently
handle a mix of structural and behavioral constructs.

Icarus Verilog is not aimed at being a simulator in the traditional sense, but
a compiler that generates code employed by back-end tools.

No objections to rename from <gdt>