./cad/iverilog, Verilog simulation and synthesis tool (stable release version)

[ CVSweb ] [ Homepage ] [ RSS ] [ Required by ] [ Add to tracker ]

Branch: CURRENT, Version: 12.0, Package name: iverilog-12.0, Maintainer: dmcmahill

Icarus Verilog is intended to compile ALL of the Verilog HDL as described in
the IEEE-1364 standard. Of course, it's not quite there yet. It does currently
handle a mix of structural and behavioral constructs.

Icarus Verilog is not aimed at being a simulator in the traditional sense, but
a compiler that generates code employed by back-end tools.


Required to build:
[devel/gperf] [pkgtools/cwrappers]

Master sites:

Filesize: 2924.898 KB

Version history: (Expand)

CVS history: (Expand)


   2024-09-26 09:45:30 by Thomas Klausner | Files touched by this commit (4) | Package removed
Log message:
iverilog: remove patches that were removed from distinfo during update
   2024-09-21 23:04:39 by Makoto Fujiwara | Files touched by this commit (3) 
Log message:
(cad/iverilog) Updated to 12.0.0

Stable version 12.0
 This is the first release in the Version 12 branch.
   2024-05-18 16:49:59 by Makoto Fujiwara | Files touched by this commit (1) 
Log message:
(cad/iverilog) Fix build, adjust WRKSRC
   2024-05-06 00:34:01 by Thomas Klausner | Files touched by this commit (1) | Package updated
Log message:
iverilog: update HOMEPAGE/MASTER_SITES
   2021-10-26 12:04:17 by Nia Alarie | Files touched by this commit (63) 
Log message:
cad: Replace RMD160 checksums with BLAKE2s checksums

All checksums have been double-checked against existing RMD160 and
SHA512 hashes
   2021-10-07 15:20:33 by Nia Alarie | Files touched by this commit (63) 
Log message:
cad: Remove SHA1 hashes for distfiles
   2020-09-27 15:48:21 by Makoto Fujiwara | Files touched by this commit (2) 
Log message:
(cad/iverilog) Fix build, adapting to bison 3.7.1
   2020-03-26 03:37:14 by Joerg Sonnenberger | Files touched by this commit (8) 
Log message:
Fix racy bison use. Rename patch to match patched file.