./cad/veriwell, Verilog Simulator

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Branch: CURRENT, Version: 2.8.7, Package name: veriwell-2.8.7, Maintainer: pkgsrc-users

VeriWell is a full Verilog simulator. It supports nearly all of the
IEEE1364-1995 standard, as well as PLI 1.0.

Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in
the mid-1990 and was included with the Thomas and Moorby book.


Required to build:
[pkgtools/cwrappers]

Master sites:

SHA1: 9ef4e6a25a4fd65db325a89ed89b199547fabbd6
RMD160: 3d86c40b353f701d61cab301e0f7c3ec136c88e7
Filesize: 855.074 KB

Version history: (Expand)


CVS history: (Expand)


   2020-05-20 08:09:10 by Roland Illig | Files touched by this commit (52)
Log message:
mark packages that fail with -Werror=char-subscripts

These packages are susceptible to bugs when confronted with non-ASCII
characters.

See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94182.

It takes some time to analyze and fix these individually, therefore they
are only marked as "needs work".
   2020-03-18 18:45:25 by Joerg Sonnenberger | Files touched by this commit (3)
Log message:
Not really C++11 ready. Don't define bool/true/false for C++.
   2016-10-09 15:14:06 by Kamil Rytarowski | Files touched by this commit (4)
Log message:
Import veriwell-2.8.7 as cad/veriwell

VeriWell is a full Verilog simulator. It supports nearly all of the
IEEE1364-1995 standard, as well as PLI 1.0.

Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in
the mid-1990 and was included with the Thomas and Moorby book.