./cad/MyHDL-iverilog, Icarus Verilog cosimulation support for py-MyHDL

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Branch: pkgsrc-2016Q1, Version: 0.8.1, Package name: MyHDL-iverilog-0.8.1, Maintainer: pkgsrc-users

MyHDL is a Python package for using Python as a hardware
description language. Popular hardware description languages, like
Verilog and VHDL, are compiled languages. MyHDL with Python
can be viewed as a "scripting language" counterpart of such
languages. However, Python is more accurately described as a very
high level language (VHLL). MyHDL users have access to the
amazing power and elegance of Python for their modeling work.


Required to run:
[cad/verilog]

Required to build:
[devel/gperf]

Master sites:

SHA1: 9b34a04c57166d99df4eec74bd8c2201e8736cd0
RMD160: da08bb105e58a13a5fa22320c8d4e7efda5d1b02
Filesize: 565.754 KB

Version history: (Expand)