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devel/yosys,
Yosys Open SYnthesis Suite
Branch: CURRENT,
Version: 0.46,
Package name: yosys-0.46,
Maintainer: thorpejThe Yosys Open SYnthesis Suite is a framework for RTL synthesis tools. It
currently has extensive Verilog-2005 support and provides a basic set of
synthesis algorithms for various application domains.
Master sites:
Filesize: 2971.77 KB
Version history: (Expand)
- (2024-10-15) Updated to version: yosys-0.46
- (2024-10-04) Updated to version: yosys-0.45nb1
- (2024-09-07) Updated to version: yosys-0.45
- (2024-04-15) Updated to version: yosys-0.38nb4
- (2024-04-15) Updated to version: yosys-0.38nb3
- (2024-03-28) Updated to version: yosys-0.38nb2
CVS history: (Expand)
2024-10-22 13:29:50 by Jason R Thorpe | Files touched by this commit (1) |
Log message:
Set USE_CXX_FEATURES to c++17, as this is the language variant specified
in the Yosys documentation.
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2024-10-22 07:31:32 by Jason R Thorpe | Files touched by this commit (1) |
Log message:
Revert previous; I mis-read the documentation.
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2024-10-22 07:30:01 by Jason R Thorpe | Files touched by this commit (1) |
Log message:
c++ -> c++17, which is what Yosys documents as the build requirement.
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2024-10-15 03:32:59 by Jason R Thorpe | Files touched by this commit (4) |
Log message:
Update to yosys-0.46.
Changes:
Various
=======
* Added new "functional backend" infrastructure with three example
backends (C++, SMTLIB and Rosette).
* Added new coarse-grain buffer cell type "$buf" to RTLIL.
* Added "-y" command line option to execute a Python script with
libyosys available as a built-in module.
* Added support for casting to type in Verilog frontend.
New commands and options
========================
* Added "clockgate" pass for automatic clock gating cell insertion.
* Added "bufnorm" experimental pass to convert design into
buffered-normalized form.
* Added experimental "aiger2" and "xaiger2" backends, and an
experimental "abc_new" command
* Added "-force-detailed-loop-check" option to "check" pass.
* Added "-unit_delay" option to "read_liberty" pass.
Verific support
===============
* Added left and right bound properties to wires when using
specific VHDL types.
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2024-10-04 05:49:38 by Ryo ONODERA | Files touched by this commit (237) |
Log message:
*: Recursive revbump from Boost 1.86.0
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2024-09-08 20:52:41 by Thomas Klausner | Files touched by this commit (1) |
Log message:
yosys: add pkg-config to TOOLS to fix build
Some cleanup while here.
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2024-09-08 17:31:21 by Jason R Thorpe | Files touched by this commit (1) | |
Log message:
Fix a patch checksum (I forgot to run "make makedistinfo" after making
a small fix before committing the update).
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2024-09-07 04:10:29 by Jason R Thorpe | Files touched by this commit (7) |
Log message:
Update to yosys-0.45.
Lots of upstream changes since 0.38. Go read here:
https://github.com/YosysHQ/yosys/releases
|