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./wip/prjtrellis, Documenting the Lattice ECP5 bit-stream format

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Branch: CURRENT, Version: 1.2.1, Package name: py310-prjtrellis-1.2.1, Maintainer: lloyd

Project Trellis enables a fully open-source flow for ECP5 FPGAs using
Yosys for Verilog synthesis and nextpnr for place and route. Project
Trellis itself provides the device database and tools for bitstream
creation.

Master sites:

https://github.com/YosysHQ/

Version history: (Expand)

(2023-02-13) Package has been reborn
(2022-11-01) Package added to pkgsrc.se, version py310-prjtrellis-1.2.1 (created)