./wip/yosys, Yosys is a framework for Verilog RTL synthesis

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Branch: CURRENT, Version: a44cc7a, Package name: yosys-a44cc7a, Maintainer: pkgsrc-users

Yosys currently has extensive Verilog-2005 support and provides a basic set of
synthesis algorithms for various application domains.

Required to run:
[lang/tcl] [devel/libffi] [devel/readline] [devel/py-mercurial] [lang/python37]

Required to build:

Master sites:

Version history: (Expand)